Performance of Deeply-Scaled, Power-Constrained Circuits

1. Introduction Power has become a primary design constraint in digital integrated circuits. Most designs in sub-100nm technologies will either maximize the performance under power constraints or minimize the energy for required amount of computation. To achieve the optimality in power-performance space, integrated circuits have to be optimized at all levels of hierarchy: device, circuit, microar-chitecture and system architecture. The system power and performance requirements have to be propagated from the system specification all the way to the technology. In order to make optimal tradeoffs at one level of the design hierarchy , the designer must know the power-performance dependencies from the lower level [1]. At the system level, for example, performance can be traded off for power and area (cost) through adding functional units or increasing the parallelism at the system level. At the microarchitecture level, this tradeoff between the power and throughput/latency exists in the choice of paral-lelism level or pipelining depth. Logic designers can optimize the delay of a circuit block by optimizing its structure: for example a carry lookahead adder is faster than the ripple carry adder, but consumes more power. At the circuit level, delay and power can be traded off through sizing and the choice of supply and threshold voltages. These tradeoffs propagate all the way to the device level, where the devices can be optimized through the choice of transistor thresholds, oxide thickness, doping concentrations and profiles.